Integrated circuit memory devices are often organized into rows and columns of memory cells, with the rows and columns separately selected based on the value of the portions of the memory address which represent row and column addresses. In such devices, the term "word lines" generally refers to a set of conductors of which one, when active, selects the addressed row of memory cells; the term "bit lines" generally refers to a set of conductors which communicate data between memory cells in the addressed row and a sense amplifier. The sense amplifier is a circuit which senses the data state of the data on an associated bit line, and which generally amplifies the sensed data state for communication to output stages of the circuit.
The sense amplifier of such memory circuits is generally called upon to sense a small differential voltage between a pair of bit lines to which the selected memory cell is connected. For purposes of speed, each of the bit lines in the the pair are generally precharged to a predetermined voltage and equalized by connecting the bit lines in the pair together for a brief period after the precharge operation. In conventional static random access memories ("SRAMs"), a pull-up device is connected between each of the bit lines and a power supply, such pull-up devices desirable to assist in pulling one of the bit lines in the bit line pair high while the other of the bit lines in the bit line pair is pulled low, the choice of which bit line goes high depending upon the sensed data state of the addressed memory cell. In a BiCMOS SRAM, a bipolar transistor is preferably used as the pull-up device as it will act as a diode clamp for the bit lines (holding the higher of the bit lines in the bit line pair at a voltage which is at least one diode drop below the positive power supply level) with a fast switching characteristic.
However, the diode characteristic of the bipolar pull-up device presents a problem in the event that noise is present on the positive (V.sub.cc) power supply to which the pull-up transistors are connected. Positive noise on V.sub.cc will pull both bit lines to a higher voltage, while negative noise on V.sub.cc will not affect the voltage of the bit lines, due to the bipolar pull-up transistor acting as a diode. After a "bump" of positive noise on V.sub.cc pulls both bit lines to a higher level, a read cycle will cause one of the bit lines in the bit line pair to be pulled low, with the other of the bit lines to remain at the bumped voltage. A failure may occur in the next cycle after the bump if the positive bump is sufficiently large that the precharge and equalization operation, i.e., the pull-up of the bit lines by the pull-up transistors, is insufficient to fully equalize the bit lines at the end of the cycle. In the case of a fully static RAM, such a failure occurs when the bit line differential voltage due to the noise is sufficiently large that the memory cell has insufficient time to establish the bit line voltages in the correct polarity.
It is therefore an object of this invention to provide a bit line pull-up circuit which has a bipolar pull-up device, but which is tolerant of perturbations of the biasing power supply.
A write operation to a particular memory cell is generally accomplished by pulling one of the bit lines of the bit line pair to a low level (V.sub.ee), while pulling the other of the bit lines to a high voltage level (V.sub.cc -V.sub.be). After the write cycle, the bit lines must again be pulled-up by the bipolar pull-up transistors to the same potential relative to one another in preparation for a read cycle thereafter. The large differential voltage of the bit lines after the write, however, requires either very large pull-up devices, or a long period of time for pulling up, either of which is not desirable.
It is therefore a further object of this invention to provide a bit line pull-up circuit which reduces the bit line differential voltage during a write cycle, speeding the recovery of the bit lines to an equalized voltage thereafter.
It is a further object of this invention to provide such a pull-up circuit incorporated in BiCMOS technology.
It is a further object of this invention to provide such a pull-up circuit in a configuration of one sense amplifier per column of memory cells.
It is a further object of this invention to provide such a pull-up circuit which both reduces the bit line differential voltage and also provides for improved tolerance of perturbations at the V.sub.cc power supply.
Other objects and advantages of the instant invention will become apparent to one of ordinary skill in the art having reference to the following specification, in conjunction with the accompanying drawings.